Experienced AMS Design Verification Engineer

About the role

Apple’s Advanced Technology group in London is seeking an experienced AMS Design Verification Engineer to ensure bug‑free first silicon for mixed‑signal designs. You will work on pre‑silicon verification, building self‑checking environments and collaborating closely with analog and digital design teams.

Key responsibilities

• Develop verification environments using SystemVerilog and UVM for multi‑layer mixed‑signal systems.
• Create test scenarios, assertions, and performance‑ and power‑analysis models.
• Execute gate‑level verification for power and timing, and support lab bring‑up activities.
• Deliver test suites to design and test engineering teams.
• Research and innovate verification techniques to improve efficiency and quality.

Required profile

• Strong knowledge of SystemVerilog test‑bench language and UVM.
• Hands‑on experience with constrained‑random verification environments.
• Background in design analysis and object‑oriented programming.
• Proficiency in English.

Required skills

• SystemVerilog
• UVM (Universal Verification Methodology)
• Object Oriented Programming
• C++
• Python
• Verilog
• FPGA emulation platforms
• Assertion Based Verification
• AI/ML (desired)

What we offer

• Opportunity to work on cutting‑edge mixed‑signal silicon that reaches millions of customers.
• Collaborative environment within Apple’s innovative Advanced Technology group.
• Access to research resources and the chance to shape verification methodologies.