Senior FPGA Design Engineer – Satellite Communications

About the role

We are seeking a Senior FPGA / RTL Design Engineer to join a cutting‑edge satellite communications team in Southampton. The role is hybrid (2 days onsite) and offers a competitive salary of around £70,000 plus bonus, equity and private medical benefits.

Key responsibilities

• Translate signal‑processing algorithms into efficient FPGA and ASIC hardware architectures.
• Develop RTL code in Verilog or SystemVerilog and drive it through synthesis, timing closure and optimisation.
• Validate designs on space‑qualified FPGA devices and integrate them with system‑level hardware.
• Collaborate with algorithm, systems and verification engineers across the full development lifecycle.
• Participate in hardware debugging, performance analysis and documentation.

Required profile

• Proven experience in high‑performance FPGA or ASIC development for digital signal processing.
• Strong understanding of timing closure, synthesis and hardware optimisation techniques.
• Ability to work independently and as part of a multidisciplinary engineering team.
• Experience in the aerospace or wireless communications domain is a plus.

Required skills

• Verilog / SystemVerilog
• FPGA design and implementation
• ASIC design flow
• High‑speed digital hardware / DSP implementation
• Timing analysis and closure
• Python (optional)
• UVM (optional)
• AMBA protocols (optional)

What we offer

• Hybrid working model (2 days onsite, 3 days remote).
• Salary range £65,000‑£75,000 per year.
• Performance bonus, equity participation and private medical scheme.
• Opportunity to work on pioneering 5G satellite infrastructure.
• Collaboration with leading UK communications engineers.