Principal Engineer, Design Verification

About the role

Analog Devices is looking for a Principal Engineer, Design Verification to define, develop and implement verification solutions for mixed-signal ICs across the full development cycle, from concept through product release. The role sits within the CSS team, which leads markets in sensing and signal processing solutions such as capacitive sensing, optical image stabilisation, power management and audio. It is based in the United Kingdom (Newbury or Edinburgh) or Valencia, Spain, with about 10% travel required.

Key responsibilities

• Verify complex designs and sub-systems using leading-edge verification methodologies, and influence the choice of methods and strategies.
• Develop testbench architectures using UVM or formal-based approaches, and define verification plans, functional coverage, tests and methodology for block and chip-level verification.
• Work with the design team on verification plans and closure metrics, debug gate-level simulation and waive timing violations approved by the designer.
• Interact continuously with analog co-simulation and firmware teams, and mentor junior verification engineers on SoC verification.
• Support post-silicon verification with design, product evaluation and applications engineering.
• Lead IP or SoC verification efforts, estimate effort, schedule projects, assign tasks, report to management or customers and build small verification teams.

Required profile

• Bachelor's or master's degree in Engineering (Electronic Engineering) or equivalent; 10-15 years in ASIC design verification.
• Experience in both IP and SoC level verification, and as a verification lead with customer-facing experience.
• Strong English speaking and writing, and building and leading small verification teams.
• Preferred: hardware emulation or FPGA prototyping, low-power methodologies (UPF), behavioural modelling of analogue circuits, processor-based design verification, and knowledge of AHB/APB/AXI/I2C/SPMI interfaces.

Required skills

• System Verilog, formal verification, constrained-random and assertion-based techniques, and coverage analysis.
• UVM testbenches, integrated into a chip-level UVM environment.
• Debugging and analytical skills.
• Scripting tools such as Makefile, Python, TCL/tclsh and Perl.