Digital Verification Engineer, Crypto & Security

About the role

NXP is expanding its Crypto & Security Competence Centre (CCC&S) in Glasgow and is looking for digital verification engineers who work on next-generation security technologies such as Post-Quantum Cryptography (PQC), secure SoC subsystems including next-generation roots of trust, and high-assurance cryptographic accelerators. The role sits alongside a transformation that integrates AI into IC design and verification flows, blending AI-driven approaches with traditional methods.

Key responsibilities

• Verify digital hardware architectures.
• Create, review and maintain verification plans, and track verification progress.
• Specify and develop verification strategies, tests and environments for security features and hardware co-processors.
• Introduce emerging verification methodologies into existing verification flows.
• Contribute to AI-driven verification automation, intelligent debug and analysis, automated test and vPlan generation, and AI-assisted RTL understanding and coverage closure.

Required profile

• BSc. or MSc. degree in Electronics or Electrical Engineering.
• Experience with SystemVerilog for testbench development and verification.
• Experience in UVM, including components, sequences, drivers, monitors and scoreboards.
• Solid understanding and practical use of Constrained Random Verification.
• Experience with Metrics-Driven Verification, including functional coverage and verification planning.
• Demonstrated success in achieving coverage closure and in analysing coverage results to refine test strategies.
• Strong debugging skills across simulations and complex verification environments.
• Knowledge of Formal Verification methods is advantageous.

Required skills

• SystemVerilog and UVM
• Constrained Random Verification
• Metrics-Driven Verification and functional coverage
• Writing SystemVerilog Assertions (SVA)
• Coverage closure and debugging